Sequential Circuits Drumtraks - Correction of I/O Address Annotations in the Service Manual
posted on 04 June 2026, updated on 09 June 2026
Summary
During reverse-engineering and hardware verification of a Sequential Circuits Drumtraks, I found that the I/O address annotations printed on the commonly circulated schematic appear to be incorrect.
The actual hardware decoding performed by U214 (74LS138) does not match the annotated addresses shown on the schematic.
This conclusion is based on:
- Continuity measurements on a real Drumtraks motherboard.
- Verification of the LS138 address decoder wiring.
- Verification of all LS138 output destinations.
- Analysis of the OS v0.5 ROM.
- Analysis of the keyboard/LED scan circuitry built around the 4099 latches.
Hardware Verification
U214 Address Decoder
U214 is a HD74LS138P (standard 74LS138).
Continuity measurements performed directly on the motherboard confirm:
| U214 Pin | Function | Connected To |
|---|---|---|
| 1 | A | Z80 A2 (pin 32) |
| 2 | B | Z80 A3 (pin 33) |
| 3 | C | Z80 A4 (pin 34) |
| 6 | G1 | Z80 A7 (pin 37) |
| 5 | /G2B | Z80 /M1 through LS04 inverter |
The /M1 path was verified:
Z80 pin 27 (/M1)
→
74LS04 pin 5
74LS04 pin 6
→
U214 pin 5 (/G2B)
Therefore the LS138 is enabled only during I/O cycles and not during instruction fetches.
LS138 Output Verification
Continuity measurements confirm:
| LS138 Output | Pin | Signal |
|---|---|---|
| Y0 | 15 | /OLEDS |
| Y1 | 14 | /OSINK |
| Y2 | 13 | /ODAC |
| Y3 | 12 | /OTRIGB |
| Y4 | 11 | /OTRIGA |
| Y5 | 10 | /OMISC |
| Y6 | 9 | /OSHMUX |
| Y7 | 7 | /OCNTR |
All outputs were verified on the physical motherboard.
LS138 Truth Table
Because:
| A | = | Z80 A2 |
| B | = | Z80 A3 |
| C | = | Z80 A4 |
and because the 74LS138 selects outputs according to:
| C | B | A | Output |
|---|---|---|---|
| 0 | 0 | 0 | Y0 |
| 0 | 0 | 1 | Y1 |
| 0 | 1 | 0 | Y2 |
| 0 | 1 | 1 | Y3 |
| 1 | 0 | 0 | Y4 |
| 1 | 0 | 1 | Y5 |
| 1 | 1 | 0 | Y6 |
| 1 | 1 | 1 | Y7 |
the actual decoded ports are:
| Address | Function |
|---|---|
| E0 | /OLEDS |
| E4 | /OSINK |
| E8 | /ODAC |
| EC | /OTRIGB |
| F0 | /OTRIGA |
| F4 | /OMISC |
| F8 | /OSHMUX |
| FC | /OCNTR |
Note that A6, A5, A1 and A0 are not decoded.
Therefore each function responds to multiple port addresses.
The addresses shown above are simply the canonical addresses used by the firmware.
Comparison with Published Schematic Annotations
Many copies of the Drumtraks schematic contain annotations similar to:
/OSHMUX @ E4H /OMISC @ E8H /OTRIGA @ ECH /OTRIGB @ F0H /OSINK @ F8H /OLEDS @ FCH
These annotations are inconsistent with the verified hardware decoding.
The corrected table is:
| Signal | Annotated Address | Verified Address |
|---|---|---|
| /OLEDS | FCH | E0H |
| /OSINK | F8H | E4H |
| /ODAC | F4H | E8H |
| /OTRIGB | F0H | ECH |
| /OTRIGA | ECH | F0H |
| /OMISC | E8H | F4H |
| /OSHMUX | E4H | F8H |
| /OCNTR | E0H | FCH |
Probable Cause of the Error
The annotated addresses appear to have been calculated assuming:
LS138 A <- A4 LS138 B <- A3 LS138 C <- A2
while the actual motherboard wiring is:
LS138 A <- A2 LS138 B <- A3 LS138 C <- A4
This produces exactly the observed reversal.
ROM Analysis (OS v0.5)
The ROM starts with:
0000: 3E 0F LD A,0FH 0002: D3 E4 OUT (E4H),A 0004: ED 56 IM 1
Initially this seemed to suggest that E4H must correspond to /OSHMUX.
However hardware verification proves that:
E4H → /OSINK
The first firmware output therefore targets the keyboard/LED scan circuitry.
Understanding the First OUT (E4H)
/OSINK drives the W/D (Write/Disable) inputs of two addressable latches:
U105 = 4099 U107 = 4099
The byte written to E4H is decoded as:
0FH = 00001111
For U107:
Address = 111 Data = 1
Therefore:
Q7 <- 1
A particularly interesting detail is that:
Q7(U107)
→
RES(U105)
RES(U107)
Thus the first firmware output immediately establishes a known reset state for the scan latches.
This makes far more sense than the previous assumption that E4H controlled the sample-and-hold multiplexer.
Conclusion
The physical motherboard, continuity measurements, LS138 truth table, and firmware analysis all support the following I/O map:
| Port | Function | Hardware Controlled |
|---|---|---|
| E0H | OLEDS | Two 4042 latch circuits (U102 and U103) driving the LED matrix |
| E4H | OSINK | Two 4099 addressable latches controlling the LED matrix (U105) and switch matrix (U107) |
| E8H | ODAC | 7524 DAC digital-to-analog converter (U226) |
| ECH | OTRIGB | Hex D-type Flip-Flop 4174 - Trigger Latch B (U219) |
| F0H | OTRIGA | Hex D-type Flip-Flop 4174 - Trigger Latch A (U217) |
| F4H | OMISC | Hex D-type Flip-Flop 4174 - Misc Output Latch (U216) |
| F8H | OSHMUX | Hex D-type Flip-Flop 4174 - Sample & Hold Address / Strobe Latch (U218) |
| FCH‑FFH | OCNTR | Intel 8253 Programmable Interval Timer (U211) |
The commonly circulated schematic annotations appear to contain a systematic reversal of the LS138 address bit order.
Additional Note Regarding the 8253 Timer (U211)
Unlike the other decoded devices, the Intel 8253 Programmable Interval Timer occupies four consecutive I/O addresses:
| Address | Function |
|---|---|
| FCH | Counter 0 |
| FDH | Counter 1 |
| FEH | Counter 2 |
| FFH | Control Register |
This is possible because the LS138 output OCNTR only generates the chip-select signal for U211.
The lower address bits A0 and A1 are connected directly to the 8253 address inputs and are therefore used internally by the timer to select one of its four registers.
Consequently, all addresses from FCH through FFH activate the same device (U211), while the specific operation performed depends on the values present on address lines A0 and A1.
This behavior differs from the other Drumtraks I/O devices, which ignore address lines A0 and A1 and therefore respond identically to all four addresses within their decoded address range.
Observations Regarding U212 (74LS04)
During the verification process, an additional discrepancy was found between the published schematic annotations and the actual motherboard wiring around U212 (74LS04).
Continuity measurements confirmed:
Z80 pin 27 (/M1)
→
U212 pin 5
U212 pin 6
→
U214 pin 5 (/G2B)
and:
U216 pin 12
→
U212 pin 13
U212 pin 12
→
CC OUT (via R222)
The available schematic annotations appear to interchange these two inverter sections.
While this discrepancy does not affect circuit operation, it demonstrates that some annotations in the available documentation should be independently verified against the physical hardware.